1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly a one transistor, one capacitance type dynamic MOS (metal oxide semiconductor).RAM (random access memory) device, as well as the process for producing the same.
2. Description of the Prior Art
Conventionally, the most common type of MOS.RAM cells are those in which one MOS transfer gate is combined with one memory capacitor utilizing a so called MOS capacitor. In such type of MOS.RAM cell, the memory capacitor is situated on the same surface of a semiconductor substrate as the transfer gate and occupies a considerable area of 30% or more of the memory cell. Since a constant electrical potential must be supplied to the MOS capacitor from outside of the memory cell, the layout of the elements of the memory device is limited due to the existence of a metal line for supplying the potential to the MOS capacitor.
A dual polycrystalline silicon process, which is employed for the production of the MOS capacitor and the transfer gate, makes the production process of the memory cell complicated, because insulation between the two layers of polycrystalline silicon and a very accurate photolithography process are required. The production yield of the memory cell is decreased, due to the dual polycrystalline silicon structure, from that of the yield of the conventional MOS.RAMs.
Furthermore, the low yield of the MOS.RAMs is attributed mainly to a thin oxide film of the capacitor, which oxide film covers a large surface area of the semiconductor substrate, because such an oxide film is liable to be defective, and further, a gate-oxide short circuit is liable to be caused by fine particles on the silicon of the semiconductor substrate. In addition, stored charges are liable to leak through a path on the substrate surface, which path is formed due to an accidentally contaminated surface portion of the substrate.
A semiconductor memory device, other than that utilizing the MOS capacitor mentioned above, is known from U.S. Pat.No. 4,003,036, in which device a junction capacitance created by a buried diffusion layer in the semiconductor substrate is utilized for a memory capacitor. The memory device disclosed in the U.S. patent mentioned above is a so called VMOS transistor and eliminates all the drawbacks of the memory device utilizing the MOS capacitor. However, a special etching process required for the formation of the V grooves causes a low production yield of the VMOS transistor, which is a problem. In addition, special caution must be taken to prevent the disconnection of the metal lines due to the steep V grooves. It is, therefore, difficult to use conventional aluminum wiring and the like, due to the steep V grooves. Furthermore, the production process of the VMOS transistor and layout of the elements of such transistor cannot be modified freely, which is another disadvantage.